1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Background Art
FIGS. 7A and 7B illustrate data outputting and data inputting in a conventional, typical semiconductor memory device.
As shown in FIG. 7A, in the conventional semiconductor memory device, data stored in a memory cell 1 passes through a sense amplifier 3 and it is output from an output buffer 5. Here, output buffer 5 includes a preamplifier 7 and a main amplifier 9, and preamplifier 7 outputs a signal DBR.
As shown in FIG. 7B, in the conventional semiconductor memory device, data is input to memory cell 1 through an input buffer 11. Here, input buffer 11 outputs a signal DBW.
FIG. 8 shows memory cell arrangement using a quarter pitch in the conventional semiconductor memory device, in which a white circle indicates a memory cell connected to a bit line BL and storing data and a black circle indicates a memory cell connected to a bit line /BL and storing inverted data.
The memory cell array includes blocks A and B formed of normal cells and blocks C and D formed of spare cells SC. Even when a normal cell storing data (or inverted data) is replaced by a spare cell SC storing inverted data (or data), for example, when block A is replaced by block D having different cell arrangement, data has been read and written as it is.
However, when blocks A and B are replaced by blocks D and C, respectively, in FIG. 8, replaced spare cell SC stores the inverted data of data stored in the normal cell. Therefore, the stress imposed during a test cannot be applied to spare cell SC under the same condition as the normal cell.